The invention relates to an integrated circuit arrangement in MOS-technology with field-effect transistors, comprising at least one test circuit which also employs MOS-technology and field-effect transistors, the test connection or connections of said test circuit being externally accessible, via which connections at least parts of the integrated circuit arrangement can be tested when a test signal is applied, and each field-effect transistor is connected to ground or to a negative voltage with its substrate connection.
Such integrated circuit arrangements are generally known. If these arrangements comprise a multitude of transistors, for example in MOS-technology with field-effect transistors, a precise analysis of faults made during fabrication, in order to eliminate the faults, is often difficult. For this purpose it is known to construct the integrated circuit in the so-called IC arrangement, which may comprise for example 16 or 24 connections, and to connect certain points of the circuit arrangement, via further integrated circuit arrangements, to the external connections in such a way that the circuit arrangement can be tested by means of test signals. Literature relating to this subject is the following: AFIPS Conference Proceedings, 1967 Spring Joint Computer Conference 30, pages 743 to 756, entitled "A structural theory of machine diagnosis" by Ramamoorthy and a publication by the same author in the "Journal of the Association for Computing Machinery" Vol. 13, no. 2 of April 1966, pages 211 to 222. From these two references it is known to divide a very intricate integrated circuit arrangement, especially one developed for microprocessors, in such a way that separate blocks are formed, between which the so-called internal connection points are located, which in their turn are then connected, either directly or via further integrated circuits, to the connections in such a way that for the purpose of testing the individual parts well-defined signals are produced on these connections, in order to obtain production mounting in the so-called micro-electronic technology and in order to be able to ascertain on which points an erroneous signal appears or in order to be able to ascertain in which part of the complex integrated circuit arrangement faults have been made during fabrication.
Furthermore, it is known from the book by "U. Tietze and Ch. Schenk", "Halbleiter-Schaltungstechnik", 4th edition 1978, inter alia pages 77 et seq, what types of field-effect transistors exist, how the circuit symbols for the types are and how said field-effect transistors are to be operated.
If such test points are not provided, the fabrication of such complex integrated circuit arrangements must be followed by a sorting operation in which as a result of the occurrence of various defects many IC's are rejected so that only a few IC's are left, for example only 10% of the total production. In order to increase this low yield, the aforementioned test circuits have been developed and are already in use, permitting the effective location and elimination of faults during fabrication, so that a substantially higher yield can be achieved, reject percentages being obtained which, depending on the size of the circuit arrangement, may for example be 10% and smaller.
In the known test method, which is also used by the Applicant, the test signal is always applied to an integrated circuit arrangement with the same polarity with which the integrated circuit arrangement is operated during its normal use. This means that when so-called n-channel field-effect transistors have been employed, the operating voltages for the normal IC are then 0 on the ground connection and a positive supply voltage of for example +5 V, +12 V or +15 V. For MOS-technology only the +5 V voltage is used in most cases. The test voltage which should now be applied to the connections for testing these IC's then also has the same direction, i.e. positive test voltage pulses are applied to the various connections and on other connections, depending on the structure of the circuit arrangement, these test voltages are available, so that it can be determined whether these test signals exhibit the correct waveform or not. During fabrication it is also possible to have access to the so-called internal connection points and to ascertain in which parts of such a circuit arrangement faults occur. For this purpose it is known to provide an additional connection for the application of the test signal, which connection is not necessary for the normal operation of the IC, i.e. a connection which is to be provided in addition to the normally available connections, solely for the purpose of testing.